1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having a plurality of memory cell arrays and being accessible bit by bit. More specifically, the present invention relates to a multiport memory used for image data processing, having a random access memory port which can be accessed at random and a serial access memory port which can only be accessed serially.
2. Description of the Background Art
In the field of image information processing and the like, image information processed or to be processed is displayed on a CRT (Cathode Ray Tube) display. In such a case, a memory, called a frame buffer, storing image information of 1 frame is often used. When a general dynamic random access memory (DRAM) is used as the frame buffer, data must be continuously read from the DRAM during the display period in order to form video signals to be displayed on the screen of the CRT display.
In a common DRAM, 1 memory cycle is defined either as a read cycle or a write cycle. Therefore, during the display period, an arithmetic processing apparatus (CPU) for carrying out arithmetic operations on image data can not access the DRAM, and the access period of the CPU to the frame buffer is limited in the horizontal or vertical blanking period other than display period. Consequently, wait time of the CPU is increased, and execution of the program becomes slower.
In order to overcome such a drawback of the common DRAM used as the frame buffer, a memory called a dual port RAM has come to be widely used as a video RAM for image processing.
The dual port RAM has an input/output port which can be accessed at random from the CPU, and a serial input/output port for serially reading data to be displayed under the control of a CRT display controller to apply the same to the CRT display. In the dual port RAM, when data of 1 row (corresponding to data of 1 horizontal scanning) are transferred from a RAM port (memory portion which can be accessed at random) to a SAM port (memory portion which can only be accessed serially), data to be displayed are read from the SAM port during the display period while the CPU can access the RAM port. This reduces the wait time of the CPU, increasing the speed of execution of the program. In the SAM port, the transferred data of 1 row are serially read, so that access time in the SAM port can be reduced to about 1/4 or 1/5 that of the RAM port, enabling display of images at high speed.
FIG. 1 schematically shows a whole structure of a conventional dual port RAM having a 256K word.times.4 bit structure. Referring to FIG. 1, the conventional dual port RAM comprises four memory cell arrays 100a, 100b, 100c and 100d. Although not specifically shown, each of the memory cell arrays 100a to 100d has a plurality of memory cells (for example, 256K bits) arranged in a matrix of M rows.times.N columns (for example, 512 rows .times.512 columns).
Provided are an address buffer 1 receiving externally applied address signals A0 to A8 to generate internal address signals for accessing the memory cell arrays 100a to 100d at random; row decoders 5a, 5b, 5c and 5d provided corresponding to each of the memory cell arrays 100a to 100d, responsive to internal row address signals from the address buffer 1 to select corresponding rows of the memory cell arrays; column decoders 6a, 6b, 6c and 6d provided corresponding to each of the memory cell arrays 100a to 100d, responsive to internal column address signals from the address buffer 1 to generate signals for selecting corresponding columns (bit lines) of the memory cell arrays; and I/O gates 7a, 7b, 7c and 7d provided corresponding to each of the memory cell arrays 100a to 100d, responsive to column select signals from the corresponding column decoders to connect selected columns of the corresponding memory cell arrays to a RAM input/output buffer 2.
The RAM input/output buffer 2 is connected to data input/output terminals DQa, DQb, DQc and DQd. The address buffer 1 time-divisionally receives external row address signals and column address signals, and generates internal row address signals and internal column address signals at prescribed timings. In a data writing mode, the RAM input/output buffer 2 buffers and applies data applied to the data input/output terminals DQa to DQd to each of the I/O gates 7a to 7d. In a data reading mode, the RAM input/output buffer 2 buffers data signals transmitted through the I/O gates 7a to 7d to transmit the same to data input/output terminals DQa to DQd, respectively. Namely, in the structure shown in FIG. 1, the semiconductor memory device is capable of inputting/outputting data 4 bits by 4 bits, and each of the memory cell arrays 100a to 100d stores 1 bit of the data bits.
In order to enable serial accessing, the semiconductor memory device further comprises data registers 9a, 9b, 9c and 9d provided corresponding to each of the memory cell arrays 100a to 100d having storage capacity enough to store data (N bits) of one row of the corresponding memory cell array; transfer gates 8a, 8b, 8c and 8d provided between the memory cell arrays and the data registers, respectively for providing data transfer paths between the corresponding memory cell arrays and the data registers; selectors 11a and 11b provided common to 2 data registers, responsive to a selection clock signal from a pointer 15 to generate a signal for selecting a corresponding bit of the data register; and SAM I/O gates 10a, 10b, 10c and 10d provided corresponding to each of the data registers 9a to 9d, responsive to the bit selecting signals from the selectors 11a and 11b for connecting the selected bits of the corresponding data registers to a SAM input/output buffer 3.
The pointer 15 generates signals for successively and serially selecting bits of the data registers from the corresponding columns of the data registers 9a to 9d, in response to internal column address signals from the address buffer 1 and to clock signals from a timing generator 4, to apply the same to the selectors 11a and 11b. The SAM input/output buffer 3 is connected to SAM data input/output terminals SQa, SQb, SQc and SQd. The SAM input/output buffer 3 inputs/outputs 4 bits of data in parallel. Therefore, each of the SAM I/O gates 10a to 10d provides a path for inputting/outputting each bit of the serial data in one to one correspondence. The reference numeral 200 denotes a semiconductor chip.
In order to define internal operation timing of the semiconductor memory device, a timing generator 4 is provided which receives signals RAS, CAS, DT/OE, WE, SC and SE and generates various internal clocks. The signal RAS is a signal for providing a timing to take row address signals in the device and defining operation timing of a row selecting circuitry. The signal CAS is a signal for providing a timing to take column address signals in the device and defining operation timing of a column selecting circuitry in this device. The signal DT/OE is a signal for providing timing of data transfer between the memory cell arrays 100a to 100d and the corresponding data registers 9a to 9d, which signal is also used as an output enable signal in the semiconductor memory device.
The signal WE is used to set the semiconductor memory device to a writing mode. The signal SE enables the SAM port for carrying out serial data access. The signal SC provides an input/output timing of the data in the SAM port and, more specifically, it provides timing for the serial selecting operation in the selectors 11a and 11b. Namely, the pointer 15 designates a bit position of the data register which is selected at first, based on the column address signal from the address buffer 1, and selects bits of the data register by shifting bit by bit successively in response to the signal SC, starting from the designated bit position. Namely, the pointer 15 and the selectors 11a and 11b maybe regarded as one shift register, and the signal SC provides timing of shifting of the shift register. The operation will be described in the following.
Input/output of data in the RAM port is done in the same manner as in a common DRAM. Namely, the address signals A0 to A8 are multiplexed time divisionally to be applied to the address buffer 1. The address signals applied to the address buffer 1 are decoded by the row decoders 5a to 5d and by the column decoders 6a to 6b in response to the signals RAS and CAS, respectively. Consequently, a 1 bit memory cell is selected in each of the memory cell arrays 100a to 100d. Designation of data writing is done by setting the control signal WE to "L", while designation of data reading operation is done by setting the control signal DT/OE to "L". In data writing operation, data applied to the RAM data input/output terminals DQa to DQd are converted into internal data through the input/output buffer 2, and thereafter they are stored in the selected memory cells, respectively, through the I/O gates 7a to 7d. In data reading, the data of the selected memory cells are applied to the input/output buffer 2 through the I/O gates 7a to 7d, and the internal data signals are converted into corresponding output data signals to be applied to the data input/output terminals DQa to DQd.
The data input/output operation in the SAM port will be described.
Reading of data from the SAM port is also carried out by the row address signals transferring data of 1 row from the memory cell arrays 100a to 100d to the corresponding data registers 9a to 9d, under the control of the address signals A0 to A8 and the signals RAS, CAS, DT/OE and WE. On this occasion, the column signal strobed in response to the signal CAS is loaded to the pointer 15. The bits (1 bit from each of the memory cell arrays 100a to 100d, total 4 bits) designated by the column address signal loaded in the pointer 15 are the first bit which are to be transmitted to the SAM input/output buffer 3 from the registers 9a and 9d.
Then, when the signal SC (Serial Control) is toggled, the content of the pointer 15 is incremented under the control of the timing generator 4, and the content in each data registers 9a to 9d are successively transmitted bit by bit to the SAM input/output buffer 3 through the selectors 11a and 11b.
Writing of data to the SAM memory portion is reversed to the above described reading operation. Every time the control signal SC attains to "H", the 4 bit data applied to the SAM input/output buffer 3 are successively written to the data registers 9a to 9d. After the data of 1 row are written in each of the data registers 9a to 9d, by opening the transfer gates 8a to 8d by the signals RAS, CAS, DT/OE and WE, the data from the corresponding data registers are written to the rows of the memory cell arrays 100a to 100d designated by the row address signals A0 to A8. The operation mode in the SAM port, that is, whether it is the reading mode or the writing mode, is determined by the direction of internal transfer carried out last time.
The internal transfer operation will be briefly described with reference to FIGS. 2 and 3, showing signal waveforms of the operation.
Referring to FIG. 2, a read transfer cycle, that is, data transfer from the RAM port to the SAM port will be described. In a data reading cycle, when the signal DT/OE is set to "L", the signal WE is set to "H" and the signal SE is set to an arbitrary state with the signal RAS being active "L", then, after the completion of data reading in the memory cell arrays 100a to 100d, that is, after the data of the memory cells connected to the selected row in the memory cell arrays 100a to 100d are transmitted to the bit lines (columns) and established, the transfer gates 8a to 8d are opened in response to the rise of the signal DT/OE, and the data are transferred to the data registers 9a to 9d to be latched therein.
For the data of 1 row transmitted to the data registers 9a to 9d, the column address signal strobed to the address buffer 1 in response to the signal CAS is loaded to the pointer 15 and designates the first bit of the data registers 9a to 9d to be outputted to the SAM input/output buffer 3 through the selectors 11a and 11b.
Data reading from the SAM input/output buffer is generally carried out after the completion of data transfer to the data registers 9a to 9d, in response to the control signal SC, SE. Consequently, data of 1 bit (total 4 bits) selected from each of the memory cell arrays 100a to 100d is read from the input/output terminals SQa to SQd in response to the control signal SC.
A write transfer cycle operation in which data are transferred from the SAM port to the RAM port will be described with reference to FIG. 3. In accordance with the same timing as in the read transfer cycle, if the signal WE is set to "L", the signal DT/OE is set to "L" and the signal SE to "L" with the signal RAS being active "L", the transfer gates 8a to 8d are opened in response to the rise of the signal DT/OE, and the contents written in the data registers 9a to 9d are written at one time to the selected rows of the memory cell arrays 100a to 100d. The write transfer cycle is generally carried after the completion of data writing to the data registers 9a to 9d from the SAM input/output buffer 3.
In the write transfer cycle, when the signal RAS attains to the active "L" level and the signal SE is at "H", a pseudo write (masked write) transfer cycle is carried out. In the pseudo write transfer cycle, the transfer gates 8a to 8d are kept closed, and data transfer from the data registers 9a to 9d to the memory cell arrays 100a to 100d is not carried out. The pseudo write transfer cycle is carried out simply to switch the SAM port from the output mode to the input mode, since the operation mode of the SAM port is defined by the internal transfer cycle carried out in the last cycle.
If the signal SE is at "H", the SAM input/output buffer is not activated, so that data writing to the data registers 9a to 9d is not carried out.
As described above, in a conventional semiconductor memory device, registers for storing memory cell data of 1 row are provided corresponding to the memory cell arrays, and exchange of data between the memory cell array and external devices is done through the data registers in order to increase the speed of reading/writing of data.
However, inthe conventional structure, the data registers and the memory cell arrays are provided in one to one correspondence. The data register 9a is capable of transferring data only with the memory cell array 100a, for example, and data transfer to other memory cell arrays is impossible. Namely, the correspondence between the memory cell arrays, the SAM data input/output terminals SQa to SQd and the RAM data input/output terminals DQa to DQd are uniquely fixed.
Therefore, if 1 bit from each of the memory cell arrays 100a to 100d, that is, a total of 4 bits of data, forms 1 pixel, and the color or the light and shade of the displayed image is to be changed, the pixel data must be changed (rearranged) by using an external device. So, the device structure for changing the color or the light and shade becomes complicated, which prevents flexible changing of the color or the light and shade.
Let us assume that in image processing, three memory cell arrays correspond to R (Red), G (Green) and B (Blue), respectively and the remaining one memory cell array is used as an unused area or a working area. If the area displayed in red is to be displayed in green and the shape of the area displayed in red is to be changed, the data of the memory cell array corresponding to red must be transferred to the array corresponding to green, while the data of the memory cellarray of red must be rewritten.
However, in a conventional semiconductor memory device, data transfer between memory cell arrays can not be directly carried out, and the data must be once read from the data register, transferred outside the device to be stored in a buffer memory for operation, for example, and the red information must be written from the buffer memory to the desired memory cell array of green. Accordingly, data transfer between memory cell arrays can not be carried out at high speed, and consequently, desired image processing can not be done at high speed.
One example of a structure for reading data serially from the SAM port on real time in a dual port RAM is disclosed in U.S. Pat. No. 4,636,986. In this prior art, disclosed is a structure in which data registers (shift registers) provided for each of a plurality of memory arrays are cascade connected. However, data transfer at one time between different data registers is not carried out.